View MCP2120-IP_7511923.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2007 microchip technology inc. ds21618b-page 1 mcp2120 features ? supports with irda ? physical layer specification (version 1.3) ? uart to ir encoder/decoder - interfaces with irda compliant transceivers - used with any uart, including standard 16550 uart and microcontroller uart ? transmit/receive formats supported: -1.63s ? hardware or software baud rate selection - up to irda standard 115.2 kbaud operation - up to 312.5 kbaud operation (at 20 mhz) - low power mode ? pb-free packaging cmos technology ? low-power, high-speed cmos technology ? fully static design ? low voltage operation ? commercial and industrial temperature ranges ? low power consumption - < 1 ma @ 3.3v, 8 mhz (typical) - 3 ma typical @ 5.0v when disabled pin diagrams block diagram pdip, soic mcp2120 v dd osc1/clkin osc2 reset rxir txir mode v ss en tx rx baud0 baud1 baud2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 decode tx txir rx rxir en mcp2120 logic baud rate baud2 generator baud1 baud0 mode encode infrared encoder/decoder
mcp2120 ds21618b-page 2 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21618b-page 3 mcp2120 1.0 device overview this document contains device specific information for the following device: ? mcp2120 this device is a low-cost, hi gh-performance, fully-static infrared encoder/decoder. this device sits between a uart and an infrared (ir) optical transceiver. the data received from a standard uart is encoded (modulated), and output as electrical pulses to the ir transceiver. the ir transceiver also receives data which it outputs as electrical pulses. the mcp2120 decodes (demodulates) these electrical pulses and then the data is transmitted by the mcp2120 uart. this modulation and demodulation method is performed in accordance with the irda standard. typically a microcontroller interfaces to the ir encoder/ decoder. infrared communication is a wireless two-way data connection using infrared light generated by low-cost transceiver signaling technology. this provides reliable communication betwe en two devices. infrared technology offers: ? universal standard for connecting portable computing devices ? easy, effortless implementation ? economical alternative to other connectivity solutions ? reliable, high speed connection ? safe to use in any environment; can even be used during air travel ? eliminates the hassle of cables ? allows pc?s and non-pc?s to communicate to each other ? enhances mobility by allowing users to easily connect 1.1 applications the mcp2120 is a stand?alone irda encoder/decoder product. figure 1-1 shows a typical application block diagram. ta b l e 1 - 2 shows the pin definitions in the user (normal) mode of operation. table 1-1: mcp2120 features overview figure 1-1: system block diagram features mcp2120 serial communications: uart, ir baud rate selection: hardware/software low power mode: yes resets: (and delays) wake-up (drt) packages: 14-pin dip 14-pin soic encode decode tx txir rx rxir en mcp2120 micro? tx rx optical uart txd rxd power down baud rate baud2 generator baud1 baud0 mode i/o controller logic (s/w mode) transceiver
mcp2120 ds21618b-page 4 ? 2007 microchip technology inc. table 1-2: pin description user mode pin name pin number pin type buffer type pdip soic description v dd 1 1 ? p positive supply for logic and i/o pins osc1/clkin 2 2 i cmos oscillator crystal input/external clock source input osc2 3 3 o ? oscillator crystal output reset 4 4 i st resets the device rxir 5 5 i st asynchronous receive from infrared transceiver txir 6 6 o ? asynchronous transmit to infrared transceiver mode 7 7 i ttl selects the device mode (data/command) for software baud rate operation. for mo re information see section 2.4.1.2 ?soft- ware selection? . baud2 8 8 i ttl baud2:baud0 specify the baud rate of the device, or if the device operates in software baud rate mode. for more informa- tion see section 2.4.1 ?baud rate? . baud1 9 9 i ttl baud0 10 10 i ttl rx 11 11 o ? asynchronous transmit to controller uart tx 12 12 i ttl asynchronous receive from controller uart en 13 13 i ? device enable. v ss 14 14 ? p ground reference for logic and i/o pins legend: ttl = ttl compatible input st = sc hmitt trigger input with cmos levels i = input o = output p = power cmos = cmos compatible input
? 2007 microchip technology inc. ds21618b-page 5 mcp2120 2.0 device operation the mcp2120 is a low cost infrared encoder/decoder. the baud rate is user selectable to standard irda baud rates between 9600 baud to 115.2 kbaud. the maxi- mum baud rate is 312.5 kbaud. 2.1 power-up any time that the device is powered up, the device reset timer delay ( parameter 32 ) must occur before any communication with the de vice is initiated. this is from both the infrared transceiver side as well as the controller uart interface. 2.2 device reset the mcp2120 is forced into the reset state when the reset pin is in the low state. after the reset pin is brought to a high state, the device reset timer occurs. once the drt times out, normal operation occurs. 2.3 bit clock the device crystal is used to derive the communication bit clock (bitclk). there are 16 bitclks for each bit time. the bitclks are used for the generation of the start bit and the eight data bits. the stop bit uses the bitclk when the data is transmitted (not for recep- tion). this clock is a fixed frequency, and has minimal varia- tion in frequency (specified by crystal manufacturer). 2.4 uart interface the uart interface commun icates with the "control- ler". this interface is a ha lf duplex interface, meaning that the system is either tr ansmitting or receiving, but not both at the same time. 2.4.1 baud rate the baud rate for the mcp2120 can be configured either by the state of three hardware pins (baud2, baud1, and baud0) or through software selection. 2.4.1.1 hardware selection three device pins are used to select the baud rate that the mcp2120 will transmit and receive data. these pins are called baud2, baud1, and baud0. there is one pin state (device mode) where the application soft- ware can specify the baud rate. table 2-1 shows the baud rate configurations. table 2-1: hardware baud rate selection vs. frequency baud2:baud0 frequency (mhz) bit rate 0.6144 (1) 2.000 3.6864 4.9152 7.3728 14.7456 (2) 20.000 (2) 000 800 2604 4800 6400 9600 19200 26042 f osc / 768 001 1600 5208 9600 12800 19200 38400 52083 f osc / 384 010 3200 10417 19200 25600 38400 78600 104167 f osc / 192 011 4800 15625 28800 38400 57600 115200 156250 f osc / 128 100 9600 31250 57600 78600 115200 230400 312500 f osc / 64 note 1: an external clock is recommended for frequencies below 2 mhz. 2: for frequencies above 7.5 mhz, the txir pulse width ( parameter ir121 ) will be shorter than the minimum pulse width of 1.6 s in the irda standard specification.
mcp2120 ds21618b-page 6 ? 2007 microchip technology inc. 2.4.1.2 software selection when the baud2:baud0 pins are configured as ? 111 ? the mcp2120 defaults to a baud rate of f osc / 768. to place the mcp2120 into command mode, the mode pin must be at a low level. when in this mode, any data that is received by the mcp2120?s uart is "echoed" back to the controller and no encoding/ decoding occurs. the echoed data will be skewed less than 1 bit time (see parameter ir141 ). when the mode pin goes high, the device is returned to data mode where the encoder/decoder is in operation. table 2-2 shows the software hex commands to config- ure the mcp2120?s baud rate. the mcp2120 receives data bytes at the existing baud rate. when the change baud rate command (0x11) is received, the last valid baud rate value received becomes the new baud rate. the new baud rate is effective after the stop bit of the echoed data. figure 2-2 shows this sequence. 2.4.2 transmitting when the controller sends serial data to the mcp2120, the baud rates are required to match. there will be some jitter on the detection of the high to low edge of the start bit. this jitter will affect the place- ment of the encoded start bit. all subsequent bits will be 16 bitclk times later. 2.4.3 receiving when the controller receives serial data from the mcp2120, the baud rates are required to match. there will be some jitter on the detection of the high to low edge of the start bit. this jitter will affect the place- ment of the decoded start bit. all subsequent bits will be 16 bitclk times later. figure 2-1: data/command mode flow table 2-2: software baud rat e selection vs. frequency mode pin goes low data mode command mode controller sends baud mcp2120 echoes baud controller sends 0x11 mcp2120 echoes 0x11 new baud rate mode pin goes high data mode when echoing the data, once the first bit is detected, it is echoed back. this means that the echoed data is skewed no more than 1 bit time. the new baud rate can occur once the echoed stop bit completes. hex command (3, 4) frequency (mhz) bit rate 0.6144 (1) 2.000 3.6864 4.9152 7.3728 14.7456 (2) 20.000 (2) 0x87 800 2604 4800 6400 9600 19200 26042 f osc / 768 0x8b 1600 5208 9600 12800 19200 38400 52083 f osc / 384 0x85 3200 10417 19200 25600 38400 78600 104167 f osc / 192 0x83 4800 15625 28800 38400 57600 115200 156250 f osc / 128 0x81 9600 31250 57600 78600 115200 230400 312500 f osc / 64 note 1: an external clock is recommended for frequencies below 2 mhz. 2: for frequencies above 7.3728 mhz, the txir pulse width ( parameter ir121 ) will be shorter than the 1.6 s irda standard specification. 3: command 0x11 is used to change to the new baud rate. 4: all other command codes are reserved for possible future use.
? 2007 microchip technology inc. ds21618b-page 7 mcp2120 2.5 modulation when the uart receives data to be transmitted, the data needs to be modulated. this modulated signal drives the ir transceiver module. figure 2-2 shows the encoding of the modulated signal. each bit time is comprised of 16-bit clocks. if the value to be transmitted (as determined by the tx pin) is a logic low, then the txir pin will output a low level for 7-bit clock cycles, a logic hi gh level for 3-bit clock cycles, and then t he remaining 6-bit clock cycles will be low. if the value to transmit is a logic high, then the txir pin will output a low level for the entire 16-bit clock cycles. 2.6 demodulation the modulated signal from the ir transceiver module needs to be demodulated to form the received data. as demodulation occurs, the bit value is placed on the rx pin in uart format. figure 2-3 shows the decoding of the modulated signal. each bit time is comprised of 16 bit clocks. if the value to be received is a logic low, then the rxir pin will be a low level for the first 3-bi t clock cycles, and then the remaining 13-bit clock cycles will be high. if the value to be received is a logic high, then the rxir pin will be a high level for the entire 16-b it clock cycles. the level on the rx pin will be in the appropriate state for the entire 16 clock cycles. figure 2-2: encoding figure 2-3: decoding bitclk tx txir 0100 0 1 16 clk start bit data bit 0 data bit 1 data bit 2 data bit... 7 clk 12 tosc bitclk rx rxir 0100 0 1 1.6 s 13 clk (or 50.5 s typical) 16 clk 16 clk 16 clk 16 clk 16 clk 16 clk 16 clk 8 clk start bit data bit 0 data bit 1 data bit 2 data bit ... (clk)
mcp2120 ds21618b-page 8 ? 2007 microchip technology inc. 2.7 encoding/decoding jitter and offset figure 2-4 shows the jitter and offset that is possible on the rx pin and the txir pin. jitter is the possible variation of the desired edge. offset is the propagation del ay of the input signal (rxir or tx) to the output signal (rx or txir). the first bit on the output pin (on rx or txir) will show jitter compared to the input pin (rxir or tx), but all remaining bits will be a constant distance. 2.8 minimizing power the device can be placed in a low power mode by disabling the device (holding the en pin at the low state). the internal state machine is monitoring this pin for a low level, and once this is detected the device is disabled and enters into a low power state. 2.8.1 returning to operation when the device is disabled, the device is in a low power state. when the en pin is brought to a high level, the device will return to the operating mode. the device requires a delay of 1000 t osc before data may be transmitted or received. figure 2-4: effects of jitter and offset tx jitter 3 clk bitclk rxir rx tx txir 16 clk 16 clk 3 clk 16 clk rx jitter tx offset rx offset 16 clk
? 2007 microchip technology inc. ds21618b-page 9 mcp2120 3.0 development tools the mcp212x developer?s daughter board is used to evaluate and demonstrate the mcp2122 or the mcp2120 irda ? standard encoder/decoder devices. a header allows the mcp212x developer?s daughter board to be jumpered easily into systems for development purposes. the mcp212x developer?s daughter board is designed to interface to several of the ?new? low cost pic ? demo boards. these include the picdem hpc explorer demo board, the picdem fs usb demo board, and the picdem lcd demo board. when the mcp212x developer?s daughter board is used in conjunction with the picdem hpc explorer demo board, the mcp212x can be connected to either of the pic18f8772's two uarts or the rx and tx sig- nals can be "crossed" so the mcp212x device can communicate directly out the picdem hpc explorer demo board's uart (db-9). features: ? 8-pin socket for inst allation of mcp2122 (installed) and 14-pin socket for installation of mcp2120 ? three optical transceiver circuits (1 installed) ? headers to interface to low cost picdem demo boards, including: - ? picdem? hpc explorer demo board - ? picdem? lcd demo board - ? picdem? fs usb demo board - ? picdem? 2 plus demo board ? headers to easily connect to the user?s embedded system ? jumpers to select routing of mcp212x signals to the picdem? demo board headers ? jumpers to configure the operating mode of the board the mcp2120/mcp2150 developer?s kit has been obsoleted but if you have access to one of these kits, it can be used to demonstrate the operation of the mcp2120.
mcp2120 ds21618b-page 10 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21618b-page 11 mcp2120 4.0 electrical characteristics absolute maximum ratings? ambient temperature under bias ................................................................................................. .......... ?40c to +125c storage temperature ............................................................................................................ .............. ... ?65c to +150c voltage on v dd with respect to v ss .....................................................................................................................0 to +7v voltage on reset with respect to v ss .............................................................................................................0 to +14v voltage on all other pins with respect to v ss ................................................................................. ?0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... ....700 mw max. current out of v ss pin ........................................................................................................................... .......150 ma max. current into v dd pin ........................................................................................................................... ..........125 ma input clamp current, i ik (vi < 0 or vi > v dd ) ............................................................... .................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) ............................................................... .............................................. 20 ma max. output current sunk by any output pin.......... ........................................................................... .....................25 ma max. output current sourced by any output pin.................................................................................. ...................25 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other condit ions above those indicated in the operation listings of this specificatio n is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mcp2120 ds21618b-page 12 ? 2007 microchip technology inc. figure 4-1: voltage-frequency graph, -40 c t a +85 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 2.0 81216 f max = (8.0 mhz/v) (v ddappmin -2.5v) + 4 mhz note: v ddappmin is the minimum voltage of the mcp2120 in the application.
? 2007 microchip technology inc. ds21618b-page 13 mcp2120 4.1 dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) param. no. sym characteristic min typ (1) max units conditions d001 v dd supply voltage 2.5 ? 5.5 v see figure 4-1 d002 v dr ram data retention voltage (2) 2.5 ? ? v device oscillator/clock stopped d003 v por v dd start voltage to ensure power-on reset ?v ss ?v d004 sv dd v dd rise rate to ensure power-on reset 0.05 ? ? v/ms d010 i dd supply current (3) ? ? ? ? ? ? 0.8 0.6 0.4 3 4 4.5 1.4 1.0 0.8 7 12 16 ma ma ma ma ma ma f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 3.0v f osc = 4 mhz, v dd = 2.5v f osc = 10 mhz, v dd = 3.0v f osc = 20 mhz, v dd = 4.5v f osc = 20 mhz, v dd = 5.5v d020 i pd device disabled current (3, 4) ? ? ? ? 0.25 0.25 0.4 3 4 3 5.5 8 a a a a v dd = 3.0v, 0 c t a +70 c v dd = 2.5v, 0 c t a +70 c v dd = 4.5v, 0 c t a +70 c v dd = 5.5v, ?40 c t a +85 c note 1: data in the typical (?typ?) column is based on characterization results at +25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered without losing ram data. 3: the supply current is mainly a function of the oper ating voltage and frequency. pin loading, pin rate, and temperature have an impact on the current consumption. a) the test conditions for all i dd measurements are made when device is enabled (en pin is high): osc1 = external square wave, from rail-to-rail; all input pins pulled to v ss , rxir = v dd , reset =v dd ; b) when device is disabled (en pin is low), the conditions for current measurements are the same. 4: when the device is disabled (en pin is low), current is measured with all input pins tied to v dd or v ss and the output pins driving a high or low level into infinite impedance.
mcp2120 ds21618b-page 14 ? 2007 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +85c (industrial) operating voltage v dd range as described in dc spec section 4.1 ?dc characteristics? . param no. sym characteristic min typ max units conditions input low voltage v il input pins d030 with ttl buffer vss ? 0.8v v for all 4.5 v dd 5.5v d030a vss ? 0.15v dd votherwise d031 with schmitt trigger buffer v ss ?0.2v dd v d032 reset , rxir v ss ?0.2v dd v d033 osc1 v ss ?0.3v dd v input high voltage v ih input pins ? d040 with ttl buffer 2.0 ? v dd v4.5 v dd 5.5v d040a 0.25v dd + 0.8v dd ?v dd v otherwise d041 with schmitt trigger buffer 0.8v dd ?v dd v for entire v dd range d042 reset , rxir 0.8v dd ?v dd v d043 osc1 0.7v dd ?v dd v input leakage current (1, 2) d060 i il input pins ? ? 1 a v ss v pin v dd , pin at hi-impedance d061 reset ??30av ss v pin v dd d063 osc1 ? ? 5 a v ss v pin v dd , xt, hs and lp osc configuration d070 ipur weak pull-up current 50 250 400 a v dd = 5v, v pin = v ss note 1: the leakage curr ent on the reset pin is strongly dependent on the app lied voltage level. the specified levels represent normal operating conditions. higher le akage current may be measured at different input voltages. 2: negative current is defined as coming out of the pin.
? 2007 microchip technology inc. ds21618b-page 15 mcp2120 dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +85c (industrial) operating voltage v dd range as described in dc spec section 4.1 ?dc characteristics? param no. sym characteristic min typ max units conditions output low voltage d080 v ol txir, rx ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, ?40 c to +85 c d083 osc2 ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, ?40 c to +85 c output high voltage d090 v oh txir, rx (1) v dd - 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, ?40 c to +85 c d092 osc2 v dd - 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, ?40 c to +85 c capacitive loading specs on output pins d100 c osc 2 osc2 pin ? ? 15 pf when external clock is used to drive osc1. d101 c io all input or output pins ? ? 50 pf note 1: negative current is defined as coming out of the pin.
mcp2120 ds21618b-page 16 ? 2007 microchip technology inc. 4.2 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: 4.2.1 timing conditions the temperature and vo ltages specified in ta b l e 4 - 2 apply to all timing specific ations unless otherwise noted. figure 4- 2 specifies the load conditions for the timing specifications. table 4-1: symbology table 4-2: ac temperature and voltage specifications figure 4-2: load conditions for device timing specifications 1. tpps2pps 2. tpps t f frequency t time e error lowercase letters (pp) and their meanings: pp io input or output pin osc oscillator rx receive tx transmit bitclk rx/tx bitclk rst reset drt device reset timer uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance ac characteristics standard operating conditions (unless otherwise stated) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range as described in dc spec section 4.1 ?dc character- istics? . p in v ss c l c l = 50 pf for all pins except osc2 15 pf for osc2 when external clock is used to drive osc1
? 2007 microchip technology inc. ds21618b-page 17 mcp2120 4.3 timing diagrams and specifications figure 4-3: external clock timing table 4-3: external clock timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ (1) max units conditions 1t osc external clkin period (2,3) 50 ? ? ns oscillator period (2) 50 ? 500 ns 1a f osc external clkin frequency (2,3) dc ? 20 mhz oscillator frequency (2) 2?20mhz 1c e clk clock error ? ? 0.01 % 3tosl, to s h clock in (osc1) low or high time 10 ? ? ns 4tosr, to s f clock in (osc1) rise or fall time ? ? 15 ns note 1: data in the typical (?typ?) column is at 5v, +25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the devi ce executing code. exceeding these specified limits may result in an unstable oscillator operation and/or hi gher than expected cu rrent consumption. when an external clock input is used, the ?max? cycl e time limit is ?dc? (no clock) for all devices. 3: a duty cycle of no more than 60/40 (high time / low time or low time / high time) is recommended for external clock inputs. osc1 q4 q1 q2 q3 q4 q1 133 44
mcp2120 ds21618b-page 18 ? 2007 microchip technology inc. figure 4-4: i/o waveform table 4-4: i/o timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ (1) max units conditions 17 tosh2iov osc1 (q1 cycle) to output valid (2) ??100ns 18 tosh2ioi osc1 (q2 cycle) to input invalid (i/o in hold time) 200 ? ? ns 19 tiov2osh input valid to osc1 (i/o in setup time) 0??ns 20 tor rx and txir pin rise time (2) ?1025ns 21 tof rx and txir pin fall time (2) ?1025ns note 1: data in the typical (?typ?) column is at 5v, +25c unless otherwise stated. 2: see figure 4-2 for loading conditions. osc1 input pin output pin q4 q1 q2 q3 17 20, 21 18 old value new value 19 note: refer to figure 4-2 for load conditions.
? 2007 microchip technology inc. ds21618b-page 19 mcp2120 figure 4-5: reset and device reset timer timing table 4-5: reset and device reset timer requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ (1) max units conditions 30 t rst l reset pulse width (low) 2000 ? ? ns v dd = 5.0 v 31 t lpt low power time-out period 9 18 30 ms v dd = 5.0 v 32 t drt device reset timer period 9 18 30 ms v dd = 5.0 v 34 tio z output hi-impedance from reset low or device reset ? ? 2 s note 1: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. v dd reset drt time-out internal reset low power timer reset 32 31 34 output pin 32 32 34 30
mcp2120 ds21618b-page 20 ? 2007 microchip technology inc. figure 4-6: usart asynchronous transmission waveform table 4-6: usart asynchronous transmission requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ max units conditions ir100 t txbit transmit baud rate hardware selection 768 ? 768 t osc baud2:baud0 = 000 384 ? 384 t osc baud2:baud0 = 001 192 ? 192 t osc baud2:baud0 = 010 128 ? 128 t osc baud2:baud0 = 011 64 ? 64 t osc baud2:baud0 = 100 software selection baud2:baud0 = 111 768 ? 768 t osc hex command = 0x87 384 ? 384 t osc hex command = 0x8b 192 ? 192 t osc hex command = 0x85 128 ? 128 t osc hex command = 0x83 64 ? 64 t osc hex command = 0x81 ir101 e txbit transmit (tx pin) baud rate error (into mcp2120) ??1% ir102 e txirbit transmit (txir pin) baud rate error (out of mcp2120) (1) ??1% ir103 t tx rf tx pin rise time and fall time ? ? 25 ns note 1: this error is not additi ve to ir101 parameter. note: refer to figure 4-2 for load conditions. ir103 tx pin ir100 ir103 ir100 ir100 ir100 start bit data bit data bit data bit
? 2007 microchip technology inc. ds21618b-page 21 mcp2120 figure 4-7: usart asynchronous receive timing table 4-7: usart asynchronous receive requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ max units conditions ir110 t rxbit receive baud rate hardware selection 768 ? 768 t osc baud2:baud0 = 000 384 ? 384 t osc baud2:baud0 = 001 192 ? 192 t osc baud2:baud0 = 010 128 ? 128 t osc baud2:baud0 = 011 64 ? 64 t osc baud2:baud0 = 100 software selection baud2:baud0 = 111 768 ? 768 t osc hex command = 0x87 384 ? 384 t osc hex command = 0x8b 192 ? 192 t osc hex command = 0x85 128 ? 128 t osc hex command = 0x83 64 ? 64 t osc hex command = 0x81 ir111 e rxbit receive (rxir pin) baud rate error (into mcp2120) ??1% ir112 e rxbit receive (rx pin) baud rate error (out of mcp2120) (1) ??1% ir113 t tx rf rx pin rise time and fall time ? ? 25 ns note 1: this error is not additi ve to ir111 parameter. note: refer to figure 4-2 for load conditions. ir112 rx pin ir112 ir110 ir110 ir110 start bit data bit data bit data bit ir110
mcp2120 ds21618b-page 22 ? 2007 microchip technology inc. figure 4-8: tx and txir waveforms table 4-8: tx and txir requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ max units conditions ir100 t txbit transmit baud rate hardware selection 768 ? 768 t osc baud2:baud0 = 000 384 ? 384 t osc baud2:baud0 = 001 192 ? 192 t osc baud2:baud0 = 010 128 ? 128 t osc baud2:baud0 = 011 64 ? 64 t osc baud2:baud0 = 100 8 software selection baud2:baud0 = 111 768 ? 768 t osc hex command = 0x87 384 ? 384 t osc hex command = 0x8b 192 ? 192 t osc hex command = 0x85 128 ? 128 t osc hex command = 0x83 64 ? 64 t osc hex command = 0x81 ir120 t tx l2 txir h tx falling edge ( ) to txir rising edge ( ) (1) 7t bitclk - 8.34 s 77t bitclk + 8.34 s t bitclk ir121 t txir pw txir pulse width 12 ? 12 t osc ir122 t txir p txir bit period (1) ?16?t bitclk note 1: t bitclk = t txbit /16 bitclk tx txir 0100 0 1 ir100 ir121 ir120 start bit data bit 7 data bit 6 data bit 5 data bit ... ir122 ir122 ir122 ir122 ir122 ir122
? 2007 microchip technology inc. ds21618b-page 23 mcp2120 figure 4-9: rxir and rx waveforms table 4-9: rxir requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ max units conditions ir110 t rxbit receive baud rate hardware selection 768 ? 768 t osc baud2:baud0 = 000 384 ? 384 t osc baud2:baud0 = 001 192 ? 192 t osc baud2:baud0 = 010 128 ? 128 t osc baud2:baud0 = 011 64 ? 64 t osc baud2:baud0 = 100 software selection baud2:baud0 = 111 768 ? 768 t osc hex command = 0x87 384 ? 384 t osc hex command = 0x8b 192 ? 192 t osc hex command = 0x85 128 ? 128 t osc hex command = 0x83 64 ? 64 t osc hex command = 0x81 ir130 t rxir l2 rx h rxir falling edge ( ) to rx falling edge ( ) (1) 8t bitclk - 8.34 s 88t bitclk + 8.34 s t bitclk ir131a t rxir pw rxir pulse width 3 ? 3 t osc ir132 t rxir p rxir bit period (1) ?16?t bitclk note 1: t bitclk = t rxbit /16 bitclk rx rxir 01 00 0 1 ir131a ir110 ir131b ir131b ir131b ir131b ir131b ir131b ir130 start bit data bit 7 data bit 6 data bit 5 data bit ... start bit data bit 7 data bit 6 data bit 5 data bit ...
mcp2120 ds21618b-page 24 ? 2007 microchip technology inc. figure 4-10: command mode: tx and rx waveforms table 4-10: tx and txir requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +85 c (industrial) operating voltage v dd range is described in section 4.1 ?dc characteristics? param. no. sym characteristic min typ max units conditions ir140a b tx transmit baud rate 16 ? 16 t bitclk ir140b b rx receive baud rate 16 ? 16 t bitclk ir141 t tx e2 rx e tx edge to rx edge (delay) 5.5 8 10.5 t bitclk ir142 t rx p2 tx s delay from rx stop bit complete to tx start bit (new baud rate) ??0t osc bitclk tx start bit data bit 7 data bit 6 data bit ... stop bit ir140b ir140b ir140b ir140b ir140b ir140b rx ir140a ir140a ir140a ir141 ir141 ir141 ir141 ir141 ir141 ir141 ir140a ir140a ir140a start bit data bit 7 ir142 (new baud rate)
? 2007 microchip technology inc. ds21618b-page 25 mcp2120 5.0 dc and ac characterist ics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables the data presented is outside specified operat ing range (e.g., outside specified v dd range). this is for information only and devices will operate properly on ly within the specified range. the data presented in this section is a st atistical summary of data collected on units from different lots over a period of time. ?typical? represents the mean of the distribution wh ile ?max? or ?min? represents (mean + 3s) and (mean ? 3s) respectively, where s is standard deviation. figure 5-1: short drt period vs. v dd 950 850 750 650 550 450 350 250 150 0 0 2.5 3.5 4.5 5.5 6.5 v dd (volts) drt period (s) max +85 c typ +25 c min ?40 c
mcp2120 ds21618b-page 26 ? 2007 microchip technology inc. figure 5-2: i oh vs. v oh , v dd = 2.5v figure 5-3: i oh vs. v oh , v dd = 5.5v figure 5-4: i ol vs. v ol , v dd = 2.5v figure 5-1: i ol vs. v ol , v dd = 5.5v 500m 1.0 1.5 v oh (volts) i oh (ma) 2.0 2.5 0 -1 -2 -3 -4 -5 -6 -7 m a x ? 4 0 c t yp + 2 5 c m i n + 8 5 c 3.5 4.0 4.5 v oh (volts) i oh (ma) 5.0 5.5 0 -5 -10 -15 -20 -25 -30 t y p + 2 5 c m in + 8 5 c m a x ? 4 0 c 25 20 15 10 5 0 250.0m 500.0m 1.0 v ol (volts) i ol (ma) min +85 c max ?40 c typ +25 c 0 50 40 30 20 10 0 500.0m 750.0m 1.0 v ol (volts) i ol (ma) 250.0m min +85 c max ?40 c typ +25 c
? 2007 microchip technology inc. ds21618b-page 27 mcp2120 6.0 packaging information 6.1 package marking information 14-lead pdip (300 mil) example: 14-lead soic (150 mil) example: xxxxxxxx xxxxxnnn yyww xxxxxxx xxxxxxx yywwnnn mcp2120 psaznnn yyww mcp2120 /sl yywwnnn legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb -free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custome r-specific information. 3 e 3 e 3 e 3 e
mcp2120 ds21618b-page 28 ? 2007 microchip technology inc. 14-lead plastic dual in-line (p) ? 300 mil body [pdip] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 14 pitch e .100 bsc top to seating plane a ? ? .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .735 .750 .775 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .045 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 n e1 d note 1 12 3 e c e b a2 l a a1 b1 b e microchip technology drawing c04-005b
? 2007 microchip technology inc. ds21618b-page 29 mcp2120 14-lead plastic small outline (sl) ? narrow, 3.90 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millmeters dimension limits min nom max number of pins n 14 pitch e 1.27 bsc overall height a ? ? 1.75 molded package thickness a2 1.25 ? ? standoff a1 0.10 ? 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 8.65 bsc chamfer (optional) h 0.25 ? 0.50 foot length l 0.40 ? 1.27 footprint l1 1.04 ref foot angle 0 ? 8 lead thickness c 0.17 ? 0.25 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 note 1 n d e e1 1 2 3 b e a a1 a2 l l1 c h h microchip technology drawing c04-065b
mcp2120 ds21618b-page 30 ? 2007 microchip technology inc. figure 6-1: embossed carrier dimensions (16 mm tape) figure 6-2: soic device to p cover tape k 0 p w b 0 a 0 table 6-1: carrier tape/cavity dimensions case outline package type carrier dimensions cavity dimensions output quantity units reel diameter in mm w mm p mm a0 mm b0 mm k0 mm sl soic .150? 14l 16 8 6.5 9.5 2.1 2600 330 us e r dir e ction of f ee d p, pitch pin 1 pin 1 r e v e rs e r ee l compon e nt ori e ntation w, width of carri e r tap e standard r ee l compon e nt ori e ntation
? 2007 microchip technology inc. ds21618b-page 31 mcp2120 appendix a: revision history revision b (february 2007) ? updated development tools section ? update packaging outline drawings ? updates product identi fication system section. revision a (march 2001) ? initial release of this document
ds21618b-page 32 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21618b-page 33 mcp2120 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device mcp2120: infrared encoder/decoder mcp2120t: infrared encoder/decoder, tape and reel temperature range i = -40c to+85c package p = plastic dip (300 mil, body), 14-lead sl = plastic soic (150 mil, body), 14-lead part no. x /xx package temperature range device examples: a) mcp2120-i/p: industrial temperature, pdip packaging b) mcp2120-i/sl: industrial temperature, soic package c) mcp2120t-i/sl: tape and reel, industrial temperature, soic package
mcp2120 ds21618b-page 34 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21618b-page 35 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, ps logo, seeval, smartsensor and the embedded control solutions company are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwar e or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development syst ems is iso 9001:2000 certified.
ds21618b-page 36 ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 12/08/06

▲Up To Search▲

Price & Availability of MCP2120-IP

	To Download MCP2120-IP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .